美国专利US20010001601A1 Delayed locked loop implementation in a synchronous dynamic random access memory

专利PDF首页>>美国专利

专利附录

专利说明

权利要求

类似技术

同族专利

引用文献

法律状态

优先权

专利摘要:
A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
公开号:US20010001601A1
申请号:US09/761,274
申请日:2001-01-16
公开日:2001-05-24
发明作者:Richard Foss；Peter Gillingham；Graham Allan
申请人:Mosaid Technologies Inc；
IPC主号:G11C11-4076

专利说明:
[0001] This invention relates to the field of semiconductor memories, and in particular to a circuit for applying a clock to a synchronous memory such as a synchronous dynamic random access memory (SDRAM). [0001] BACKGROUND TO THE INVENTION
[0002] An SDRAM, shown in block diagram in FIG. 1 typically operates as follows, with reference to the signal timing diagram shown in FIG. 2. A clock input terminal [0002] 1 receives a clock input signal CLK. The remainder of the SDRAM is represented by the memory array and support circuitry block 3. The clock signal arriving at the clock input terminal 1 is buffered inside the SDRAM, represented by the receiver 5 and buffer 6, and is distributed to internal circuitry of the SDRAM.
[0003] A signal at the output of the memory array and support circuitry [0003] 3 is applied to output buffers, represented by output buffer 8, which is enabled by the clock signal to drive data onto data terminals 10 of the SDRAM. However, due to the delays caused by the internal buffering and the interconnect wire on the integrated circuit chip that distributes the clock signal, the clock signal arrives at the enable terminal of the buffers delayed from the clock input signal. This delayed clock signal is illustrated in FIG. 2 as signal ICLK.
[0004] Assuming that the system is responsive to the rising edge of the clock signal, the delay between the rising edges is shown in FIG. 2 as internal clock skew [0004] 12. This clock skew can be a significant fraction of the clock period if the part is driven with a high frequency clock. The clock skew typically determines the maximum speed of the part. As the operating frequency of the part increases, as determined by the clock frequency, the clock skew delay causes enabling of the output buffer 8 too late relative to the next rising clock edge and the valid data at the output data terminals 10 will appear too late for the receiving chip.
[0005] Prior to the present invention, there were either of two solutions used to deal with this problem: (a) making the clock buffer circuitry between the clock input terminal [0005] 1 and the output buffer circuit enable terminal as fast as possible, and (b) using a phase locked loop (PLL) to drive the enable terminal of the output buffer.
[0006] Implementing the first solution results in a limit to the operating frequency of the part. There will always be a limit to the operating frequency of the part, because there will always be significant delay associated with the clock buffer and distribution circuitry and delays introduced by parasitic resistance and capacitance of the interconnection conductors used to distribute the buffered clock signal to the output buffers, which is evident from FIG. 1. Thus as shown in FIG. 2, after the read command to the memory array circuitry [0006] 3 from the address and control input of the memory array, to output data to the output buffers 8, there must be a delay 12 until valid data is output to the data terminals 10, as indicated by the timing diagram DQ. This time is the sum of the internal clock skew from the rising edge of the clock input signal CLK to the rising edge of the delayed clock signal ICLK, and the time from the rising edge of the clock signal ICLK to the time that valid data is output on the output terminals 10 caused by the output buffer delay after it has been clocked by the ICLK signal.
[0007] The second solution provides considerable improvement over the first. An on chip oscillator is used in a phase locked loop (PLL) which is synchronized with the input clock signal. The internal clock signal can be either multiplied in frequency or adjusted to remove internal clock skew as much as possible. [0007]
[0008] A system implementing the second solution is shown in FIG. 3, and a corresponding timing diagram is shown in FIG. 4. A PLL [0008] 15 is fed by the input clock signal from receiver 5, as well as by a feedback signal on conductor 17 derived from the interconnection conductor which distributes the output buffer enable clock signal. The latter signal is received from the output of the PLL via the internal buffering circuitry represented by buffer 6.
[0009] Thus the already buffered (and delayed) clock signal is applied to the PLL and is compared with the input clock signal. Since the operation of the PLL is to synchronize the two signals, the clock signal to be distributed to the enable inputs of the output buffers, represented by the timing diagram ICLK in FIG. 4, is made as close as possible in timing to the input clock signal. The internal clock skew is thus minimized, as illustrated by skew time [0009] 19 shown in FIG. 4. Thus the output buffer is enabled much closer to the clock edge that is received by the part and valid data appears sooner relative to the clock edge, and thus allowing higher frequency operation of the part. This is shown by access time 21, which it may be seen is much shorter than access time 12 resulting from the first solution.
[0010] However it has been found that the PLL solution also suffers from problems. It is complex, requiring an on-chip oscillator with feedback control of the frequency depending on the monitored status of the on-chip oscillator relative to the input clock. It requires significant stand-by power due to its extra circuitry, and it requires considerable start-up time for the on-chip oscillator to synchronize and lock to the input clock frequency. It also requires use of an analog oscillator in a digital circuit, which requires significantly different and complex fabrication techniques. [0010] SUMMARY OF THE INVENTION
[0011] The present invention minimizes the elapsed time between a clock edge that is input to a synchronous memory such as an SDRAM and the time at which the same clock edge eventually triggers the output buffer of the SDRAM to drive valid data onto the output terminals of the SDRAM. The present invention utilizes a delay locked loop (DLL) instead of the phase locked loop used in the second solution described above. The DLL allows higher clock frequency operation while requiring less standby current and start-up time than the system that uses the PLL. No oscillator is required as is required using the PLL, and the entire system can be fabricated using digital integrated circuit technology, rather than a mixture of analog and digital technology. [0011]
[0012] In accordance with an embodiment of the invention, a clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed fro the clock input signal, the delay being a small fraction of the clock period of the clock input signal. The fraction can be negligibly small. [0012]
[0013] In accordance with another embodiment, a clock applying circuit is comprised of a synchronous dynamic random access memory (SDRAM) comprised of a memory array and an output buffer connected to the memory array, the memory array having a clock input signal terminal and the output buffer having an enable terminal for receiving a driving clock signal, a clock input for receiving a clock input signal, a tapped delay line comprised of a series of delay elements and having an input, apparatus for applying the clock input signal to the clock input signal terminal and to the input of the tapped delay line, apparatus for receiving output signals of plural ones of the delay elements and for providing one of the output signals of the delay elements as the driving clock signal, apparatus for applying the driving clock signal to the enable terminal of the output buffer, and apparatus for selecting said one of the output signals having a predetermined one of the rising and falling edge time which follows a corresponding rising or falling edge of the clock input signal by a clock skew delay time of the SDRAM between said clock input signal terminal of the memory array and the output buffer. [0013] BRIEF INTRODUCTION TO THE DRAWINGS
[0014] A better understanding of the invention will be obtained by reading the description of the invention below, with reference to the following drawings, in which: [0014]
[0015] FIGS. 1 and 3 are block diagrams illustrating prior art systems, [0015]
[0016] FIGS. 2 and 4 are timing diagrams corresponding to and used in understanding operation of the systems of FIGS. 1 and 3 respectively, and [0016]
[0017] FIG. 5 is a block diagram illustrating an embodiment of the present invention. [0017] DETAILED DESCRIPTION OF THE INVENTION
[0018] Turning to FIG. 5, an input clock signal is applied to a tapped delay line formed of a series of delay elements [0018] 25 such as inverters. The outputs of predetermined ones of the delay elements, which can be each one of the delay elements, are provided to the inputs of a selection apparatus such as a multiplexer 27. The output of the multiplexer 29 provides a signal, referred to herein as a driving clock signal, which in this embodiment is applied to the enable terminal of the output buffer in a manner as described above with respect to the prior art systems.
[0019] A delay comparator [0019] 31 has one input that receives the input clock signal, and another input that receives the driving clock signal. The comparator 31 outputs a control signal which has a value that depends on the differential between the input clock signal and the driving clock signal. That control signal is applied to the control inputs of multiplexer 27, and determines which of the inputs to it are passed through it to output 29 and forms the driving clock signal. The value of the control signal is such that the delay between the input clock signal and the driving clock signal is minimized in the positive sense (i.e. the leading edge of the driving clock signal will always be at the same time or later than the leading edge of the input clock signal).
[0020] In this manner the output buffer of the memory will be enabled either no or a minimum time following the input clock. [0020]
[0021] In another embodiment, the feedback signal (i.e. the driving clock signal) is delayed by a delay circuit [0021] 33, referred to herein as a delay model, which use similar elements as the real circuit path taken by the input clock signal, including buffers, logic gates, interconnect conductors, etc. The result is a signal for comparison by the delay comparator 31 which is delayed by a value which tracks the real circuit's performance as operating conditions vary. It's use in a memory can allow the memory to operate at high speeds and maintains its capability as operating conditions such as temperature vary.
[0022] While the system requires some time on start-up to adapt itself to a stable operating condition, the start-up modes on most synchronous memories should be sufficient for the output buffer to receive a properly adjusted clock signal. Due to the nature of the delay locked loop, there will be a minimum frequency below which the internal function of the clock will be uncertain. If such frequencies are contemplated, external control circuitry can be used to disable the delay locked loop, such as by using a register bit which when set enables the delay locked loop and when reset disables the delay locked loop. Then the chip operates with the digital locked loop disabled, the start-up time and minimum frequency requirements will be ignored. [0022]
[0023] If the delay locked loop derived clock is used only for the output buffer, any chip mode registers can be set and data can be written to memory before the delay locked loop has adapted. If the chip enters a power down mode while retaining supply voltage levels, the last tap position can be preserved so that normal operation can be quickly re-enabled. [0023]
[0024] During a standby state of the memory, the delay locked loop can be disabled, and the delay chain settings can be maintained, as long as the power is applied, allowing the part to enter a low power mode. Upon exit from the standby state into an active state, the system will enter a faster lock since the delay chain settings are maintained. [0024]
[0025] The delay locked loop can be disabled and the regular buffered version of the system can be used as in the prior art, enabling the output buffer with the prior art form of delayed clock signal, which can allow the system to be tested or operated using a low frequency clock. [0025]
[0026] The driving clock signal can be used as the clock for the entire memory system, it can be used for only parts of the memory system and the input clock signal used for others, or can be used only to enable the output buffer with the input clock signal used for the remainder of the memory system. [0026]
[0027] The present invention is not limited for use in conjunction with an SDRAM which was used as an example, but can be used in conjunction with other synchronous memories such as synchronous static random access memories, video random access memories, synchronous graphics random access memories, synchronous read only memories. In addition, other designs of the delay locked loop may be used than the one described herein. [0027]
[0028] A person understanding this invention may now conceive of alternative structures and embodiments or variations of the above. All of those which fall within the scope of the claims appended hereto are considered to be part of the present invention. [0028]

权利要求:
Claims (10)
[1" id="US-20010001601-A1-CLM-00001] 1. A clock applying circuit for a synchronous memory comprising:
(a) a clock input for receiving a clock input signal;
(b) means connected to the synchronous memory for receiving a driving clock signal; and
(c) a tapped delay line for receiving the clock input signal and for delivering said clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay line being comprised of a series of delay elements for carrying said clock input signal;
(d) means for providing the driving clock signal from an output of one of the delay elements;
(e) means for selecting an output from said one of the delay elements comprising a comparator for comparing the clock input signal with said driving clock signal and for selecting said output from said one of the delay elements based on a closest predetermined one of a rising or falling edge of a clock input signal following an enable time required at a particular enable terminal of the synchronous memory; and
(f) means for providing the driving clock signal to said particular enable terminal.
[2" id="US-20010001601-A1-CLM-00002] 2. A clock applying circuit as defined in
claim 1 including delay model means having a signal time delay simulating clock skew delay between a clock input terminal of the synchronous memory for receiving the clock input signal and said particular enable terminal, an input port of the delay model means for receiving the driving clock signal and for providing a delayed driving signal to the comparator.
[3" id="US-20010001601-A1-CLM-00003] 3. A clock applying circuit as defined in
claim 2 in which the selecting means is comprised of a multiplexer for receiving output signals of plural ones of the delay elements at respective inputs thereof, means for receiving an input select control signal from the comparator resulting from said comparing for selecting one of said output signals for passing through the multiplexer as the driving clock signal.
[4" id="US-20010001601-A1-CLM-00004] 4. A clock applying circuit as defined in
claim 1 in which the selecting means is comprised of a multiplexer for receiving output signals of plural ones of the delay elements at respective inputs thereof and for outputting one of the output signals as the driving clock signal.
[5" id="US-20010001601-A1-CLM-00005] 5. A clock applying circuit as defined in
claim 1 in which the selecting means is comprised of a multiplexer for receiving output signals of plural ones of the delay elements at respective inputs thereof, means for receiving an input select control signal from the comparator resulting from said comparing for selecting one of said output signals for passing through the multiplexer as the driving clock signal.
[6" id="US-20010001601-A1-CLM-00006] 6. A clock applying circuit for a synchronous memory comprising:
a clock input receiving a clock input signal;
a tapped delay line receiving the clock input signal and delivering a clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay line being comprised of a series of delay elements for carrying said clock input signal; and
a selector selecting an output from said one of the delay elements to provide the driving clock signal, the selector comprising a comparator comparing the clock input signal with said driving clock signal and the selector selecting said output from said one of the delay elements based on a closest predetermined one of a rising or falling edge of a clock input signal following an enable time required at a particular enable terminal of the synchronous memory.
[7" id="US-20010001601-A1-CLM-00007] 7. A clock applying circuit as defined in
claim 1 including a delay model having a signal time delay simulating clock skew delay between a clock input terminal of the synchronous memory for receiving the clock input signal and said particular enable terminal, an input port of the delay model receiving the driving clock signal and providing a delayed driving signal to the comparator.
[8" id="US-20010001601-A1-CLM-00008] 8. A clock applying circuit as defined in
claim 7 in which the selector is comprised of a multiplexer receiving output signals of plural ones of the delay elements at respective inputs thereof, and receiving an input select control signal from the comparator resulting from said comparing for selecting one of said output signals for passing through the multiplexer as the driving clock signal.
[9" id="US-20010001601-A1-CLM-00009] 9. A clock applying circuit as defined in
claim 6 in which the selector is comprised of a multiplexer receiving output signals of plural ones of the delay elements at respective inputs thereof and for outputting one of the output signals as the driving clock signal.
[10" id="US-20010001601-A1-CLM-00010] 10. A clock applying circuit as defined in
claim 6 in which the selector is comprised of a multiplexer receiving output signals of plural ones of the delay elements at respective inputs thereof, and receiving an input select control signal from the comparator resulting from said comparing for selecting one of said output signals for passing through the multiplexer as the driving clock signal.

类似技术:

公开号 | 公开日 | 专利标题

US6205083B1|2001-03-20|Delayed locked loop implementation in a synchronous dynamic random access memory

US6205086B1|2001-03-20|Phase control circuit, semiconductor device and semiconductor memory

US6975149B2|2005-12-13|Method and circuit for adjusting the timing of output data based on an operational mode of output drivers

US6333893B1|2001-12-25|Method and apparatus for crossing clock domain boundaries

KR100662221B1|2007-01-02|Delay-locked loop with binary-coupled capacitor

US7676686B2|2010-03-09|Delay locked loop circuit and synchronous memory device including the same

US5953286A|1999-09-14|Synchronous DRAM having a high data transfer rate

US20040222829A1|2004-11-11|Delay-locked loop | capable of directly receiving external clock signals

US20010043102A1|2001-11-22|Internal clock signal generating circuit permitting rapid phase lock

US6049241A|2000-04-11|Clock skew circuit

US5987619A|1999-11-16|Input signal phase compensation circuit capable of reliably obtaining external data

US6754112B2|2004-06-22|Integrated circuit devices having delay circuits for controlling setup/delay times of data signals that are provided to memory devices

US6147527A|2000-11-14|Internal clock generator

KR100484250B1|2005-04-22|Digital dll circuit for controlling initial delay

US7676643B2|2010-03-09|Data interface device for accessing memory

US6717447B1|2004-04-06|Delay adjustment circuit

KR100474734B1|2005-07-01|Clock Generation Circuit Suitable for Synchronous Semiconductor Memory Devices

同族专利:

公开号 | 公开日

US6205083B1|2001-03-20|

US20130121096A1|2013-05-16|

US6314052B2|2001-11-06|

US6067272A|2000-05-23|

US20090316514A1|2009-12-24|

US20040130962A1|2004-07-08|

US7599246B2|2009-10-06|

US20140104969A1|2014-04-17|

US20050265506A1|2005-12-01|

US20030107944A1|2003-06-12|

US20020075747A1|2002-06-20|

US8638638B2|2014-01-28|

US6992950B2|2006-01-31|

US5796673A|1998-08-18|

US20030090952A1|2003-05-15|

US6657918B2|2003-12-02|

US8369182B2|2013-02-05|

US6657919B2|2003-12-02|

引用文献:

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

US8813345B2|2011-06-14|2014-08-26|Samsung Electro-Mechanics Japan Advanced Technology Co., Ltd.|Method for manufacturing disk drive device|

CN109428661A|2017-08-21|2019-03-05|中兴通讯股份有限公司|A kind of main clock phase alignment device and method based on FPGA|US6279116B1|1992-10-02|2001-08-21|Samsung Electronics Co., Ltd.|Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation|

US2255232A|1940-08-01|1941-09-09|Recordgraph Corp|Support for sound record films|

US3413615A|1965-09-16|1968-11-26|Ibm|Delay line buffer storage circuit|

GB1332302A|1969-11-17|1973-10-03|Rca Corp|Colour television receiver arrangement|

US4005450A|1970-05-13|1977-01-25|Hitachi, Ltd.|Insulated gate field effect transistor having drain region containing low impurity concentration layer|

US4016587A|1974-12-03|1977-04-05|International Business Machines Corporation|Raised source and drain IGFET device and method|

US4016511A|1975-12-19|1977-04-05|The United States Of America As Represented By The Secretary Of The Air Force|Programmable variable length high speed digital delay line|

US4330852A|1979-11-23|1982-05-18|Texas Instruments Incorporated|Semiconductor read/write memory array having serial access|

US4338569A|1980-03-11|1982-07-06|Control Data Corporation|Delay lock loop|

US4463440A|1980-04-15|1984-07-31|Sharp Kabushiki Kaisha|System clock generator in integrated circuit|

JPH0143464B2|1981-11-26|1989-09-20|Fujitsu Ltd||

US4511811A|1982-02-08|1985-04-16|Seeq Technology, Inc.|Charge pump for providing programming voltage to the word lines in a semiconductor memory array|

US4673829A|1982-02-08|1987-06-16|Seeq Technology, Inc.|Charge pump for providing programming voltage to the word lines in a semiconductor memory array|

US4527258A|1982-09-30|1985-07-02|Mostek Corporation|E2 PROM having bulk storage|

US4496861A|1982-12-06|1985-01-29|Intel Corporation|Integrated circuit synchronous delay line|

US4549283A|1983-09-06|1985-10-22|Rockwell International Corporation|Digital time delay circuit with high speed and large delay capacity|

US4754164A|1984-06-30|1988-06-28|Unisys Corp.|Method for providing automatic clock de-skewing on a circuit board|

US4638182A|1984-07-11|1987-01-20|Texas Instruments Incorporated|High-level CMOS driver circuit|

US4782247A|1984-08-08|1988-11-01|Fujitsu Limited|Decoder circuit having a variable power supply|

US4623805A|1984-08-29|1986-11-18|Burroughs Corporation|Automatic signal delay adjustment apparatus|

US4637018A|1984-08-29|1987-01-13|Burroughs Corporation|Automatic signal delay adjustment method|

US4604582A|1985-01-04|1986-08-05|Lockheed Electronics Company, Inc.|Digital phase correlator|

NL8500526A|1985-02-25|1986-09-16|Philips Nv|METHOD FOR ADDRESSING A MEMORY WITH A DELAY LINE WITH ANY ACCESSIBILITY AND SIGNAL PROCESSING DEVICE PROVIDED WITH SUCH A DELAY LINE.|

US4845437A|1985-07-09|1989-07-04|Minolta Camera Kabushiki Kaisha|Synchronous clock frequency conversion circuit|

US4636930A|1985-10-01|1987-01-13|Maxim Integrated Products, Inc.|Integrated dual charge pump power supply and RS-232 transmitter/receiver|

US4931992B1|1986-01-17|1998-03-03|Toshiba Kk|Semiconductor memory having barrier transistors connected between sense and restore circuits|

US4795985A|1986-04-01|1989-01-03|Hewlett-Packard Company|Digital phase lock loop|

US4813005A|1987-06-24|1989-03-14|Hewlett-Packard Company|Device for synchronizing the output pulses of a circuit with an input clock|

US4755704A|1987-06-30|1988-07-05|Unisys Corporation|Automatic clock de-skewing apparatus|

US5029136A|1987-11-25|1991-07-02|Texas Instruments Incorporated|High-speed DRAM sense amp with high noise immunity|

US5093807A|1987-12-23|1992-03-03|Texas Instruments Incorporated|Video frame storage system|

US4789996A|1988-01-28|1988-12-06|Siemens Transmission Systems, Inc.|Center frequency high resolution digital phase-lock loop circuit|

US5101117A|1988-02-17|1992-03-31|Mips Computer Systems|Variable delay line phase-locked loop circuit synchronization system|

JP2585348B2|1988-02-22|1997-02-26|株式会社東芝|Nonvolatile semiconductor memory device|

US4994688A|1988-05-25|1991-02-19|Hitachi Ltd.|Semiconductor device having a reference voltage generating circuit|

US4958091A|1988-06-06|1990-09-18|Micron Technology, Inc.|CMOS voltage converter|

DE68914197T2|1988-06-20|1994-11-10|Kumiai Chemical Industry Co|Alkanoic acid derivatives and herbicidal agents.|

US5173617A|1988-06-27|1992-12-22|Motorola, Inc.|Digital phase lock clock generator without local oscillator|

US5148399A|1988-06-28|1992-09-15|Oki Electric Industry Co., Ltd.|Sense amplifier circuitry selectively separable from bit lines for dynamic random access memory|

KR0141495B1|1988-11-01|1998-07-15|미다 가쓰시게|Semiconductor memory device and defect remedying method thereof|

US5087829A|1988-12-07|1992-02-11|Hitachi, Ltd.|High speed clock distribution system|

JP2684806B2|1989-02-03|1997-12-03|日本電気株式会社|Integrated circuit|

US5291058A|1989-04-19|1994-03-01|Kabushiki Kaisha Toshiba|Semiconductor device silicon via fill formed in multiple dielectric layers|

US4948745A|1989-05-22|1990-08-14|Motorola, Inc.|Process for elevated source/drain field effect structure|

NL8901371A|1989-05-31|1990-12-17|Oce Nederland Bv|CORONA DEVICE.|

US5258660A|1990-01-16|1993-11-02|Cray Research, Inc.|Skew-compensated clock distribution system|

US5036528A|1990-01-29|1991-07-30|Tandem Computers Incorporated|Self-calibrating clock synchronization system|

US6150855A|1990-02-06|2000-11-21|Bull, S.A.|Phase-locked loop and resulting frequency multiplier|

US5118975A|1990-03-05|1992-06-02|Thinking Machines Corporation|Digital clock buffer circuit providing controllable delay|

US5243703A|1990-04-18|1993-09-07|Rambus, Inc.|Apparatus for synchronously generating clock signals in a data processing system|

IL96808A|1990-04-18|1996-03-31|Rambus Inc|Integrated circuit i/o using a high performance bus interface|

JP2548425B2|1990-05-23|1996-10-30|シャープ株式会社|Semiconductor memory device|

US5220206A|1990-06-29|1993-06-15|Analog Devices, Inc.|Control apparatus with improved recovery from power reduction, and storage device therefor|

US5285421A|1990-07-25|1994-02-08|Advanced Micro Devices|Scheme for eliminating page boundary limitation on initial access of a serial contiguous access memory|

JP3100622B2|1990-11-20|2000-10-16|沖電気工業株式会社|Synchronous dynamic RAM|

TW198135B|1990-11-20|1993-01-11|Oki Electric Ind Co Ltd||

US5109394A|1990-12-24|1992-04-28|Ncr Corporation|All digital phase locked loop|

US5223755A|1990-12-26|1993-06-29|Xerox Corporation|Extended frequency range variable delay locked loop for clock synchronization|

US5247469A|1991-05-23|1993-09-21|Proxim, Inc.|Digital frequency synthesizer and method with vernier interpolation|

US5272729A|1991-09-20|1993-12-21|International Business Machines Corporation|Clock signal latency elimination network|

US5272390A|1991-09-23|1993-12-21|Digital Equipment Corporation|Method and apparatus for clock skew reduction through absolute delay regulation|

SE470428B|1991-11-01|1994-02-21|Asea Brown Boveri|Industrial machine safety switch|

US5295164A|1991-12-23|1994-03-15|Apple Computer, Inc.|Apparatus for providing a system clock locked to an external clock over a wide range of frequencies|

US5245231A|1991-12-30|1993-09-14|Dell Usa, L.P.|Integrated delay line|

US5206889A|1992-01-17|1993-04-27|Hewlett-Packard Company|Timing interpolator|

US5554950A|1992-02-04|1996-09-10|Brooktree Corporation|Delay line providing an adjustable delay in response to binary input signals|

US5252867A|1992-02-14|1993-10-12|Vlsi Technology, Inc.|Self-compensating digital delay semiconductor device with selectable output delays and method therefor|

JP3517237B2|1992-03-06|2004-04-12|ラムバス・インコーポレーテッド|Synchronous bus system and memory device therefor|

DE69325119T2|1992-03-19|1999-11-04|Toshiba Kawasaki Kk|Clock synchronized semiconductor memory device and access method|

US6310821B1|1998-07-10|2001-10-30|Kabushiki Kaisha Toshiba|Clock-synchronous semiconductor memory device and access method thereof|

US5384745A|1992-04-27|1995-01-24|Mitsubishi Denki Kabushiki Kaisha|Synchronous semiconductor memory device|

US5317202A|1992-05-28|1994-05-31|Intel Corporation|Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle|

US5371764A|1992-06-26|1994-12-06|International Business Machines Corporation|Method and apparatus for providing an uninterrupted clock signal in a data processing system|

KR950012019B1|1992-10-02|1995-10-13|삼성전자주식회사|Data output buffer of semiconductor memory device|

KR960003526B1|1992-10-02|1996-03-14|삼성전자주식회사|Semiconductor memory device|

JP3400824B2|1992-11-06|2003-04-28|三菱電機株式会社|Semiconductor storage device|

JP3078934B2|1992-12-28|2000-08-21|富士通株式会社|Synchronous random access memory|

US5412697A|1993-01-14|1995-05-02|Apple Computer, Inc.|Delay line separator for data bus|

US5812832A|1993-01-29|1998-09-22|Advanced Micro Devices, Inc.|Digital clock waveform generator and method for generating a clock signal|

US5544203A|1993-02-17|1996-08-06|Texas Instruments Incorporated|Fine resolution digital delay line with coarse and fine adjustment stages|

US5400370A|1993-02-24|1995-03-21|Advanced Micro Devices Inc.|All digital high speed algorithmic data recovery method and apparatus using locally generated compensated broad band time rulers and data edge position averaging|

JP3247190B2|1993-04-13|2002-01-15|三菱電機株式会社|Phase locked loop circuit and integrated circuit device|

US5552726A|1993-05-05|1996-09-03|Texas Instruments Incorporated|High resolution digital phase locked loop with automatic recovery logic|

US5337285A|1993-05-21|1994-08-09|Rambus, Inc.|Method and apparatus for power control in devices|

US5553276A|1993-06-30|1996-09-03|International Business Machines Corporation|Self-time processor with dynamic clock generator having plurality of tracking elements for outputting sequencing signals to functional units|

US5373255A|1993-07-28|1994-12-13|Motorola, Inc.|Low-power, jitter-compensated phase locked loop and method therefor|

US5479647A|1993-11-12|1995-12-26|Intel Corporation|Clock generation and distribution system for a memory controller with a CPU interface for synchronizing the CPU interface with a microprocessor external to the memory controller|

US5463337A|1993-11-30|1995-10-31|At&T Corp.|Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein|

US5406518A|1994-02-08|1995-04-11|Industrial Technology Research Institute|Variable length delay circuit utilizing an integrated memory device with multiple-input and multiple-output configuration|

JP3754070B2|1994-02-15|2006-03-08|ラムバス・インコーポレーテッド|Delay lock loop|

US5440515A|1994-03-08|1995-08-08|Motorola Inc.|Delay locked loop for detecting the phase difference of two signals having different frequencies|

US5440514A|1994-03-08|1995-08-08|Motorola Inc.|Write control for a memory using a delay locked loop|

US5384737A|1994-03-08|1995-01-24|Motorola Inc.|Pipelined memory having synchronous and asynchronous operating modes|

US5479128A|1994-03-16|1995-12-26|Industrial Technology Research Institute|Single ram multiple-delay variable delay circuit|

US5497115A|1994-04-29|1996-03-05|Mosaid Technologies Incorporated|Flip-flop circuit having low standby power for driving synchronous dynamic random access memory|

JP3177094B2|1994-05-31|2001-06-18|富士通株式会社|Semiconductor storage device|

US5714904A|1994-06-06|1998-02-03|Sun Microsystems, Inc.|High speed serial link for fully duplexed data communication|

JP3157681B2|1994-06-27|2001-04-16|日本電気株式会社|Logical data input latch circuit|

IL110181A|1994-06-30|1998-02-08|Softchip Israel Ltd|Microprocessor device and peripherals|

US5655113A|1994-07-05|1997-08-05|Monolithic System Technology, Inc.|Resynchronization circuit for a memory system and method of operating same|

US5880624A|1994-07-08|1999-03-09|Kabushiki Kaisha Toshiba|Constant potential generating circuit and semiconductor device using same|

JP3207680B2|1994-08-30|2001-09-10|株式会社東芝|Semiconductor integrated circuit|

US5828250A|1994-09-06|1998-10-27|Intel Corporation|Differential delay line clock generator with feedback phase control|

US5537068A|1994-09-06|1996-07-16|Intel Corporation|Differential delay line clock generator|

US5570054A|1994-09-26|1996-10-29|Hitachi Micro Systems, Inc.|Method and apparatus for adaptive clock deskewing|

JP2771464B2|1994-09-29|1998-07-02|日本電気アイシーマイコンシステム株式会社|Digital PLL circuit|

US5796673A|1994-10-06|1998-08-18|Mosaid Technologies Incorporated|Delay locked loop implementation in a synchronous dynamic random access memory|

KR0142970B1|1995-06-24|1998-08-17|김광호|Reference voltage generator circuit of semiconductor memory apparatus|

US5790612A|1996-02-29|1998-08-04|Silicon Graphics, Inc.|System and method to reduce jitter in digital delay-locked loops|

JP3410922B2|1996-04-23|2003-05-26|株式会社東芝|Clock control circuit|

US5777501A|1996-04-29|1998-07-07|Mosaid Technologies Incorporated|Digital delay line for a reduced jitter digital delay lock loop|

US5802005A|1996-09-23|1998-09-01|Texas Instruments Incorporated|Four bit pre-fetch sDRAM column select architecture|

US6125157A|1997-02-06|2000-09-26|Rambus, Inc.|Delay-locked loop circuitry for clock delay adjustment|

CA2204089C|1997-04-30|2001-08-07|Mosaid Technologies Incorporated|Digital delay locked loop|

US6240047B1|1998-07-06|2001-05-29|Texas Instruments Incorporated|Synchronous dynamic random access memory with four-bit data prefetch|

US6101197A|1997-09-18|2000-08-08|Micron Technology, Inc.|Method and apparatus for adjusting the timing of signals over fine and coarse ranges|

CA2223119A1|1997-11-28|1999-05-28|Mosaid Technologies Incorporated|Address counter cell|

KR100278653B1|1998-01-23|2001-02-01|윤종용|Double data rate semiconductor memory device|

US6028804A|1998-03-09|2000-02-22|Monolithic System Technology, Inc.|Method and apparatus for 1-T SRAM compatible memory|

US6327318B1|1998-06-30|2001-12-04|Mosaid Technologies Incorporated|Process, voltage, temperature independent switched delay compensation scheme|

US6185149B1|1998-06-30|2001-02-06|Fujitsu Limited|Semiconductor integrated circuit memory|

US6510503B2|1998-07-27|2003-01-21|Mosaid Technologies Incorporated|High bandwidth memory interface|

US5999474A|1998-10-01|1999-12-07|Monolithic System Tech Inc|Method and apparatus for complete hiding of the refresh of a semiconductor memory|

US6075740A|1998-10-27|2000-06-13|Monolithic System Technology, Inc.|Method and apparatus for increasing the time available for refresh for 1-t SRAM compatible devices|

US6496437B2|1999-01-20|2002-12-17|Monolithic Systems Technology, Inc.|Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory|

US6470060B1|1999-03-01|2002-10-22|Micron Technology, Inc.|Method and apparatus for generating a phase dependent control signal|

US6282606B1|1999-04-02|2001-08-28|Silicon Aquarius, Inc.|Dynamic random access memories with hidden refresh and utilizing one-transistor, one-capacitor cells, systems and methods|

US6646941B1|1999-04-30|2003-11-11|Madrone Solutions, Inc.|Apparatus for operating an integrated circuit having a sleep mode|

JP2001035153A|1999-07-23|2001-02-09|Fujitsu Ltd|Semiconductor memory|

US6240043B1|1999-12-08|2001-05-29|International Business Machines Corporation|SDRAM with a maskable input|

JP3745185B2|2000-03-13|2006-02-15|沖電気工業株式会社|Dynamic random access memory|

KR100367690B1|2000-12-04|2003-01-14|실리콘세븐|Asynchronous SRAM using DRAM cell and Operating Method thereof|

KR100490657B1|2000-12-30|2005-05-24|주식회사 하이닉스반도체|Variable control Apparatus of Memory Drivability and its method|

KR100578233B1|2000-12-30|2006-05-12|주식회사 하이닉스반도체|Variable control apparatus of data input/output in synchronous semiconductor memory device|

EP1225597A1|2001-01-15|2002-07-24|STMicroelectronics S.r.l.|Synchronous-reading nonvolatile memory|

JP2002373489A|2001-06-15|2002-12-26|Mitsubishi Electric Corp|Semiconductor memory|

US6795899B2|2002-03-22|2004-09-21|Intel Corporation|Memory system with burst length shorter than prefetch length|

US6680874B1|2002-08-29|2004-01-20|Micron Technology, Inc.|Delay lock loop circuit useful in a synchronous system and associated methods|

KR100535071B1|2002-11-07|2005-12-07|주식회사 하이닉스반도체|Self refresh apparatus|

US6912168B2|2003-03-18|2005-06-28|United Memories, Inc.|Non-contiguous masked refresh for an integrated circuit memory|

KR100522432B1|2003-04-29|2005-10-20|주식회사 하이닉스반도체|Data output controller and its method in semiconductor memory device|

US7795934B2|2003-12-11|2010-09-14|Micron Technology, Inc.|Switched capacitor for a tunable delay circuit|

US7034591B2|2004-08-30|2006-04-25|Texas Instruments Incorporated|False-lock-free delay locked loop circuit and method|

US7119589B2|2004-09-10|2006-10-10|Mediatek Incorporation|Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof|

US7327174B2|2006-03-14|2008-02-05|Intel Corporation|Fast locking mechanism for delay lock loops and phase lock loops|

JP5639740B2|2008-10-24|2014-12-10|ピーエスフォールクスコエスエイアールエルＰＳ４ＬｕｘｃｏＳ．ａ．ｒ．ｌ．|DLL circuit and control method thereof|USRE40552E1|1990-04-06|2008-10-28|Mosaid Technologies, Inc.|Dynamic random access memory using imperfect isolating transistors|

GB9007791D0|1990-04-06|1990-06-06|Foss Richard C|High voltage boosted wordline supply charge pump and regulator for dram|

GB9007790D0|1990-04-06|1990-06-06|Lines Valerie L|Dynamic memory wordline driver scheme|

US5796673A|1994-10-06|1998-08-18|Mosaid Technologies Incorporated|Delay locked loop implementation in a synchronous dynamic random access memory|

US6831493B2|1998-10-30|2004-12-14|Mosaid Technologies Incorporated|Duty cycle regulator|

US6209071B1|1996-05-07|2001-03-27|Rambus Inc.|Asynchronous request/synchronous data dynamic random access memory|

JP3929116B2|1997-07-04|2007-06-13|富士通株式会社|Memory subsystem|

WO1999019874A1|1997-10-10|1999-04-22|Rambus Incorporated|Power control system for synchronous memory device|

US6282253B1|1997-12-16|2001-08-28|Texas Instruments Incorporated|Post-filtered recirculating delay-locked loop and method for producing a clock signal|

JP3789222B2|1998-01-16|2006-06-21|富士通株式会社|DLL circuit and memory device incorporating the same|

US6154821A|1998-03-10|2000-11-28|Rambus Inc.|Method and apparatus for initializing dynamic random access memorydevices by levelizing a read domain|

US6150863A|1998-04-01|2000-11-21|Xilinx, Inc.|User-controlled delay circuit for a programmable logic device|

EP1068619B1|1998-04-01|2005-02-16|Mosaid Technologies Incorporated|Semiconductor memory asynchronous pipeline|

US6127858A|1998-04-30|2000-10-03|Intel Corporation|Method and apparatus for varying a clock frequency on a phase by phase basis|

KR100305646B1|1998-05-29|2001-11-30|박종섭|Clock correcting circuit|

US6289068B1|1998-06-22|2001-09-11|Xilinx, Inc.|Delay lock loop with clock phase shifter|

US7564283B1|1998-06-22|2009-07-21|Xilinx, Inc.|Automatic tap delay calibration for precise digital phase shift|

CA2250538A1|1998-10-30|2000-04-30|Mosaid Technologies Incorporated|Duty cycle regulator|

KR100310460B1|1998-12-30|2001-11-15|박종섭|Apparatus and method for reducing initial lock time of delay locked loop|

US6400706B1|1999-04-02|2002-06-04|Qualcomm Incorporated|System and method for re-synchronizing a phase-independent first-in first-out memory|

CA2270516C|1999-04-30|2009-11-17|Mosaid Technologies Incorporated|Frequency-doubling delay locked loop|

US6928128B1|1999-05-03|2005-08-09|Rambus Inc.|Clock alignment circuit having a self regulating voltage supply|

DE19934501C1|1999-07-22|2000-11-09|Siemens Ag|Synchronous integratedmemory e.g. dynamic random-access memory|

US6584576B1|1999-11-12|2003-06-24|Kingston Technology Corporation|Memory system using complementary delay elements to reduce rambus module timing skew|

US6765976B1|2000-03-29|2004-07-20|G-Link Technology|Delay-locked loop for differential clock signals|

JP3895520B2|2000-05-29|2007-03-22|富士通株式会社|Clock modulator|

US6448756B1|2000-08-30|2002-09-10|Micron Technology, Inc.|Delay line tap setting override for delay locked looptestability|

US6437713B1|2000-10-06|2002-08-20|Xilinx, Inc.|Programmable logic device having amplitude and phase modulation communication|

US7017070B1|2000-10-13|2006-03-21|Ati International Srl|Apparatus for synchronization of double data rate signaling|

US7061941B1|2000-11-28|2006-06-13|Winbond Electronics Corporation America|Data input and output circuits for multi-data rate operation|

JP4592179B2|2000-12-19|2010-12-01|ルネサスエレクトロニクス株式会社|DELAY-LOCKED LOOP, SEMICONDUCTOR DEVICE INCLUDING THE DELAY-LOCKED LOOP, AND CONTROL METHOD FOR SYSTEM RUNNING BY CLOCK SYNCHRONIZATION|

US6839860B2|2001-04-19|2005-01-04|Mircon Technology, Inc.|Capture clock generator using master and slave delay locked loops|

US6617894B2|2001-05-14|2003-09-09|Samsung Electronics Co., Ltd.|Circuits and methods for generating internal clock signal of intermediate phase relative to external clock|

KR100399941B1|2001-06-30|2003-09-29|주식회사 하이닉스반도체|Register controlled delay locked loop in ddr sdram|

DE10134230A1|2001-07-13|2003-01-30|Infineon Technologies Ag|Integrated semiconductor memory component with active ON/OFF signal separating circuit|

DE10136852C2|2001-07-27|2003-09-25|Infineon Technologies Ag|Method and circuit arrangement for generating a data strobe signal for very fast semiconductor memory systems|

US6556489B2|2001-08-06|2003-04-29|Micron Technology, Inc.|Method and apparatus for determining digital delay line entry point|

KR100422585B1|2001-08-08|2004-03-12|주식회사 하이닉스반도체|Ring - register controlled DLL and its method|

US6504438B1|2001-09-17|2003-01-07|Rambus, Inc.|Dual loop phase lock loops using dual voltage supply regulators|

US6621314B2|2001-09-25|2003-09-16|Intel Corporation|Delay locked loop|

US6678205B2|2001-12-26|2004-01-13|Micron Technology, Inc.|Multi-mode synchronous memory device and method of operating and testing same|

US6944040B1|2001-12-28|2005-09-13|Netlogic Microsystems, Inc.|Programmable delay circuit within a content addressable memory|

US6650575B1|2001-12-28|2003-11-18|Netlogic Microsystems, Inc.|Programmable delay circuit within a content addressable memory|

JP4231230B2|2002-02-05|2009-02-25|セイコーエプソン株式会社|Pulse waveform shaping apparatus, laser printer, pulse waveform shaping method and laser printer serial video data generation method|

DE10208715B4|2002-02-28|2004-05-06|Infineon Technologies Ag|Latency timer for an S-DRAM|

KR20040008594A|2002-07-19|2004-01-31|주식회사 하이닉스반도체|Delay locked loop|

US7110446B1|2002-07-26|2006-09-19|Xilinx, Inc.|Method and apparatus for reducing effect of jitter|

US7149874B2|2002-08-16|2006-12-12|Micron Technology, Inc.|Memory hub bypass circuit and method|

US8934597B2|2003-03-12|2015-01-13|Infineon Technologies Ag|Multiple delay locked loop integration system and method|

US7512188B1|2003-04-10|2009-03-31|Xilinx, Inc.|Phase shift keying signaling for integrated circuits|

US7477716B2|2003-06-25|2009-01-13|Mosaid Technologies, Inc.|Start up circuit for delay locked loop|

KR100543925B1|2003-06-27|2006-01-23|주식회사 하이닉스반도체|Delay Locked Loop and its method for delaying locked a clock|

DE10330593B4|2003-07-07|2010-11-04|Qimonda Ag|Integrated clock supply module for a memory module, memory module, which includes the integrated clock supply module, as well as methods for operating the memory module under test conditions|

DE602004009137T2|2003-07-31|2008-06-19|Stmicroelectronics Pvt. Ltd.|Digital clock modulator|

US6946870B1|2003-10-21|2005-09-20|Xilinx, Inc.|Control of simultaneous switch noise from multiple outputs|

CN101677244B|2003-12-11|2017-08-04|考文森智财管理公司|High output impedance charge pump for PLL/DLL|

JP2005184196A|2003-12-17|2005-07-07|Seiko Epson Corp|Delay adjustment circuit, integrated circuit device, and delay adjustment method|

DE102004009958B3|2004-03-01|2005-09-22|Infineon Technologies Ag|Circuit arrangement for latency control|

US7038519B1|2004-04-30|2006-05-02|Xilinx, Inc.|Digital clock manager having cascade voltage switch logic clock paths|

US7157951B1|2004-04-30|2007-01-02|Xilinx, Inc.|Digital clock manager capacitive trim unit|

US7046052B1|2004-04-30|2006-05-16|Xilinx, Inc.|Phase matched clock divider|

US7078950B2|2004-07-20|2006-07-18|Micron Technology, Inc.|Delay-locked loop with feedback compensation|

KR100636929B1|2004-11-15|2006-10-19|주식회사 하이닉스반도체|Data output circuit for memory device|

KR100638747B1|2004-12-28|2006-10-30|주식회사 하이닉스반도체|Clock generation apparatus in semiconductor memory device and its method|

US7190201B2|2005-02-03|2007-03-13|Mosaid Technologies, Inc.|Method and apparatus for initializing a delay locked loop|

DE102005008151B4|2005-02-23|2008-02-28|Infineon Technologies Ag|DLL circuit for providing an adjustable phase relationship to a periodic input signal|

US8134412B2|2005-03-31|2012-03-13|Urenschi Assets Limited Liability Company|Synchronization of a data output signal to an input clock|

US9171585B2|2005-06-24|2015-10-27|Google Inc.|Configurable memory circuit system and method|

US8090897B2|2006-07-31|2012-01-03|Google Inc.|System and method for simulating an aspect of a memory circuit|

US8041881B2|2006-07-31|2011-10-18|Google Inc.|Memory device with emulated characteristics|

DE112006001810T5|2005-06-24|2008-08-21|Metaram Inc., San Jose|Integrated memory core and memory interface circuitry|

US7609567B2|2005-06-24|2009-10-27|Metaram, Inc.|System and method for simulating an aspect of a memory circuit|

US8060774B2|2005-06-24|2011-11-15|Google Inc.|Memory systems and memory modules|

US10013371B2|2005-06-24|2018-07-03|Google Llc|Configurable memory circuit system and method|

US9507739B2|2005-06-24|2016-11-29|Google Inc.|Configurable memory circuit system and method|

US8359187B2|2005-06-24|2013-01-22|Google Inc.|Simulating a different number of memory circuit devices|

DE112006002300B4|2005-09-02|2013-12-19|Google, Inc.|Device for stacking DRAMs|

US20080126690A1|2006-02-09|2008-05-29|Rajan Suresh N|Memory module with memory stack|

US8089795B2|2006-02-09|2012-01-03|Google Inc.|Memory module with memory stack and interface with enhanced capabilities|

US9632929B2|2006-02-09|2017-04-25|Google Inc.|Translating an address associated with a command communicated between a system and memory circuits|

US9542352B2|2006-02-09|2017-01-10|Google Inc.|System and method for reducing command scheduling constraints of memory circuits|

US8077535B2|2006-07-31|2011-12-13|Google Inc.|Memory refresh apparatus and method|

US8244971B2|2006-07-31|2012-08-14|Google Inc.|Memory circuit system and method|

US7392338B2|2006-07-31|2008-06-24|Metaram, Inc.|Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits|

US8327104B2|2006-07-31|2012-12-04|Google Inc.|Adjusting the timing of signals associated with a memory system|

US20080025136A1|2006-07-31|2008-01-31|Metaram, Inc.|System and method for storing at least a portion of information received in association with a first operation for use in performing a second operation|

US7590796B2|2006-07-31|2009-09-15|Metaram, Inc.|System and method for power management in memory systems|

US20080028136A1|2006-07-31|2008-01-31|Schakel Keith R|Method and apparatus for refresh management of memory modules|

US7724589B2|2006-07-31|2010-05-25|Google Inc.|System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits|

US20080028137A1|2006-07-31|2008-01-31|Schakel Keith R|Method and Apparatus For Refresh Management of Memory Modules|

US8209479B2|2007-07-18|2012-06-26|Google Inc.|Memory circuit system and method|

US7386656B2|2006-07-31|2008-06-10|Metaram, Inc.|Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit|

US8796830B1|2006-09-01|2014-08-05|Google Inc.|Stackable low-profile lead frame package|

DE102006044854A1|2006-09-22|2008-03-27|Qimonda Ag|delay circuit|

US20080082763A1|2006-10-02|2008-04-03|Metaram, Inc.|Apparatus and method for power management of memory circuits by a system or component thereof|

US8055833B2|2006-10-05|2011-11-08|Google Inc.|System and method for increasing capacity, performance, and flexibility of flash storage|

US8397013B1|2006-10-05|2013-03-12|Google Inc.|Hybrid memory module|

US8130560B1|2006-11-13|2012-03-06|Google Inc.|Multi-rank partial width memory modules|

JP4324202B2|2007-01-25|2009-09-02|シャープ株式会社|A / D converter|

CN101617371B|2007-02-16|2014-03-26|莫塞德技术公司|Non-volatile semiconductor memory having multiple external power supplies|

US20080253214A1|2007-04-05|2008-10-16|Xware Technology, Inc.|Method and apparatus for incorporating DDR SDRAM into portable devices|

US7602224B2|2007-05-16|2009-10-13|Hynix Semiconductor, Inc.|Semiconductor device having delay locked loop and method for driving the same|

US8080874B1|2007-09-14|2011-12-20|Google Inc.|Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween|

US8316069B2|2007-10-12|2012-11-20|Sanyo Semiconductor Co., Ltd.|Semiconductor integrated circuit with a random number generation circuit wherein the rise and all times are variably controlled|

US8898368B2|2007-11-07|2014-11-25|Inphi Corporation|Redriven/retimed registered dual inline memory module|

US8111566B1|2007-11-16|2012-02-07|Google, Inc.|Optimal channel design for memory devices for providing a high-speed memory interface|

US8081474B1|2007-12-18|2011-12-20|Google Inc.|Embossed heat spreader|

EP2223301A4|2007-12-21|2012-04-04|Mosaid Technologies Inc|Non-volatile semiconductor memory device with power saving feature|

US8291248B2|2007-12-21|2012-10-16|Mosaid Technologies Incorporated|Non-volatile semiconductor memory device with power saving feature|

US8438328B2|2008-02-21|2013-05-07|Google Inc.|Emulation of abstracted DIMMs using abstracted DRAMs|

US8386722B1|2008-06-23|2013-02-26|Google Inc.|Stacked DIMM memory interface|

US8335894B1|2008-07-25|2012-12-18|Google Inc.|Configurable memory system with interface circuit|

KR101156031B1|2008-12-26|2012-06-18|에스케이하이닉스 주식회사|Delay circuit and variable delay circuit|

US8770890B2|2009-03-05|2014-07-08|Stormtrap Llc|Module and assembly for managing the flow of water|

DE202010017690U1|2009-06-09|2012-05-29|Google, Inc.|Programming dimming terminating resistor values|

KR101796116B1|2010-10-20|2017-11-10|삼성전자 주식회사|Semiconductor device, memory module and memory system having the same and operating method thereof|

KR20120044061A|2010-10-27|2012-05-07|에스케이하이닉스 주식회사|Delay locked loop and integrated circuit including the same|

US9143120B2|2011-12-22|2015-09-22|Intel Corporation|Mechanisms for clock gating|

KR101245088B1|2012-08-13|2013-03-18|서영호|Power generator using electrical furnace|

US9197398B2|2013-04-18|2015-11-24|Oracle International Corporation|Distributed phase-correction circuit|

US9590602B2|2014-06-13|2017-03-07|Stmicroelectronics International N.V.|System and method for a pulse generator|

US10622044B2|2017-09-22|2020-04-14|Qualcomm Incorporated|Memory hold margin characterization and correction circuit|

法律状态:
2001-10-18| STCF| Information on status: patent grant|Free format text: PATENTED CASE |

2003-07-22| DC| Disclaimer filed|Effective date: 20030127 |

2005-04-13| FPAY| Fee payment|Year of fee payment: 4 |

2009-04-08| FPAY| Fee payment|Year of fee payment: 8 |

2009-04-28| AS| Assignment|Owner name: MOSAID TECHNOLOGIES INCORPORATED, CANADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FOSS, RICHARD C.;GILLINGHAM, PETER B.;ALLAN, GRAHAM;REEL/FRAME:022597/0630;SIGNING DATES FROM 19941005 TO 19941012 |

2009-05-06| AS| Assignment|Owner name: MOSAID TECHNOLOGIES INCORPORATED, CANADA Free format text: CHANGE OF ADDRESS;ASSIGNOR:MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:022645/0149 Effective date: 20090209 |

2012-01-10| AS| Assignment|Owner name: ROYAL BANK OF CANADA, CANADA Free format text: U.S. INTELLECTUAL PROPERTY SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) - SHORT FORM;ASSIGNORS:658276 N.B. LTD.;658868 N.B. INC.;MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:027512/0196 Effective date: 20111223 |

2013-03-05| FPAY| Fee payment|Year of fee payment: 12 |

2014-03-13| AS| Assignment|Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: CHANGE OF NAME;ASSIGNOR:MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:032439/0638 Effective date: 20140101 |

2014-08-07| AS| Assignment|Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344 Effective date: 20140611 Owner name: CONVERSANT IP N.B. 276 INC., CANADA Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344 Effective date: 20140611 Owner name: CONVERSANT IP N.B. 868 INC., CANADA Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344 Effective date: 20140611 |

2014-09-03| AS| Assignment|Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA Free format text: CHANGE OF ADDRESS;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033678/0096 Effective date: 20140820 Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: CHANGE OF ADDRESS;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033678/0096 Effective date: 20140820 |

2014-09-09| AS| Assignment|Owner name: CPPIB CREDIT INVESTMENTS INC., AS LENDER, CANADA Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033706/0367 Effective date: 20140611 Owner name: ROYAL BANK OF CANADA, AS LENDER, CANADA Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033706/0367 Effective date: 20140611 |

2018-10-12| AS| Assignment|Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424 Effective date: 20180731 Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424 Effective date: 20180731 |

优先权:

申请号 | 申请日 | 专利标题

US08/319,042|US5796673A|1994-10-06|1994-10-06|Delay locked loop implementation in a synchronous dynamic random access memory|

US08/996,095|US6067272A|1994-10-06|1997-12-22|Delayed locked loop implementation in a synchronous dynamic random access memory|

US09/392,088|US6205083B1|1994-10-06|1999-09-08|Delayed locked loop implementation in a synchronous dynamic random access memory|

US09/761,274|US6314052B2|1994-10-06|2001-01-16|Delayed locked loop implementation in a synchronous dynamic random access memory|US09/761,274| US6314052B2|1994-10-06|2001-01-16|Delayed locked loop implementation in a synchronous dynamic random access memory|

US09/977,088| US20020075747A1|1994-10-06|2001-10-12|Delayed locked loop implementation in a synchronous dynamic random access memory|

US10/279,217| US6657918B2|1994-10-06|2002-10-23|Delayed locked loop implementation in a synchronous dynamic random access memory|

US10/348,062| US6657919B2|1994-10-06|2003-01-17|Delayed locked loop implementation in a synchronous dynamic random access memory|

US10/645,330| US6992950B2|1994-10-06|2003-08-21|Delay locked loop implementation in a synchronous dynamic random access memory|

US11/195,257| US7599246B2|1994-10-06|2005-08-01|Delay locked loop implementation in a synchronous dynamic random access memory|

US12/547,955| US8369182B2|1994-10-06|2009-08-26|Delay locked loop implementation in a synchronous dynamic random access memory|

US13/732,791| US8638638B2|1994-10-06|2013-01-02|Delay locked loop implementation in a synchronous dynamic random access memory|

US14/134,996| US20140104969A1|1994-10-06|2013-12-19|Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory|

[返回顶部]